Vector computation device and vector computation method

ABSTRACT

A method of determining which search target vector from a plurality of search target vectors is closest to an input vector. A device to perform the method is also disclosed. Rather then perform a distance calculation for each and every search target vector, the disclosed method narrows the field of the search through a simple process. The input vector is compared to each search target vector, and a mask is used to evaluate the result of the comparison. Then, the actual distance is calculated for those search target vectors within a search range of the input vector.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a vector computation device and avector computation method to search data close to the input vector datafrom plural vector data as a search target.

2. Description of the Related Art

When there is an input vector data possessing n-order elements, there isa general need for retrieving data close to the input vector data fromsearch target vector data. Such processing is used, for example, in acase of the middle layer which is the closest to the input data files ina neural network, conducting a resembling picture search without using acharacter index in a picture data base.

Referring to FIG. 13, an apparatus compares input vector data and searchtarget vector data. The distance calculation circuit 100 calculates eachdistance between the input vector A and plural search target vector dataB. The minimum value judgement circuit 102 selects the one which has theminimum distance between the two vectors in accordance with thecalculation result.

The distance calculation circuit 100 may calculate several distancesbetween vectors. For example, Euclidean distance and Manhattan distancemay be calculated. Suppose vector A and vector B are both n-order andelements of vector A are (A₁, A₂, . . . , A_(n)) while elements ofvector B are (B₁, B₂, . . . , B_(n)) the Euclidean distance is√{Σ(Ai-Bi)² } and the Manhattan distance is calculated by Σ|Ai-Bi|. Thedistance calculation between vectors in this manner shall be conductedbetween vector A and all search target vectors B, and the search targetvector B having the minimum distance will be extracted.

This vector search method calculates vector distances between the inputvector A and each search target vector B. This demands a heavy burdenfor processing. The Euclidean distance is particularly burdensome. Thesubtraction result for each element of the two vectors must be squared,and this is a complex calculation.

These distance calculations also require calculation between inputvector A and all of the search target vectors B, so that as the numberof search target vectors increases so does the quantity for thecalculation, causing the search time to increase. These problems becomemore noticeable as the distance calculation is conducted by software.

SUMMARY OF THE INVENTION

It is the purpose of the present invention to solve these problems byproviding a vector calculation device and a vector calculation method tonarrow the search target field through simple processing, reducing theburden for processing in searching for a vector close to the inputvector among plural search target vectors, and shortening the processingtime.

The advantages and purpose of the invention will be set forth in part inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. Theadvantages and purpose of the invention will be realized and attained bymeans of the elements and combinations particularly pointed out in theappended claims.

The present invention comprises first and second Gray code conversionmeans, first and second mask generation means, and a judgement means. Adata of certain elements in an input vector is converted to a Gray codeby the first Gray code conversion means, and a data of certain elementsin search target vector is converted to a Gray code by the second Graycode conversion means.

The first mask generating means generates first mask data. The firstmask data designates bit positions which change when Gray codescorresponding to the upper limit value and the lower limit value of thesearch target are compared. The second mask generating generates secondmask data. The second mask data designates lower bits which reflectchanges when selected elements of all vectors included in the searchrange are converted to Gray codes.

At the judgement means, a comparison between each element of the inputvector and the search target vectors is conducted for all bits exceptthose bits designated by the first and the second mask data, enabling ajudgement of whether the search condition is met or not by a simplecalculation, thereby making it possible to reduce the search targetfield with simple processing.

Each of the first and second Gray code conversion means, and each of thefirst and second mask generating means, can conduct the predeterminedconversion processing easily using a conversion table.

Another method for converting to Gray codes with simple processing is toconduct an XOR for each bit between a binary code corresponding to eachelement of the input vector and a data attained by shifting this binarycode to the right by 1 bit by the first and the second Gray codeconversion means in order to attain a corresponding Gray code.

It is also possible to configure the first mask generating means toattain the first mask data with easy processing. The first maskgenerating means comprises third and fourth Gray code conversion meansto output Gray codes corresponding to the upper limit value and thelower limit value of the search range, and a computation means toconduct an XOR for each bit of these two Gray codes.

The second mask generating means calculates an integer P wherein 2^(P-2)<74 ≦2^(p-1). The search range is from -θ to +θ centered on the inputvector element. The second mask data then includes only the lower Pbits. These first and second mask data require only one time calculationper each input vector element, so that even if there are plural searchtarget vectors, the burden for processing is light.

The present invention is also equipped with a distance calculation meansand a minimum value judgement means. A distance between two vectors iscalculated only when the search condition by the judgement meansmentioned above is meet for all elements of an input vector and a searchtarget vectors. The minimum value of the distance is judged when thereare plural search target vectors.

Therefore, compared to the case of calculating distances between all thesearch target vectors and the input vectors, a burden for searching thesearch target vector which has the minimum distance is reduced, therebyshorten the processing time.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate an embodiment of the inventionand together with the description, serve to explain the principles ofthe invention. In the drawings,

FIGS. 1(A)-1(D) show diagrams to describe an outline of the vectorcalculation method in accordance with the present invention;

FIG. 2 is a flow chart of a processing procedure showing a specificvector calculation method in accordance with the present invention;

FIG. 3 shows a specific example of a data comparison;

FIG. 4 is a chart showing a searchable range of the search target vectorby using the vector calculation method in accordance with the presentinvention;

FIG. 5 is a chart showing a searchable range of the search target vectorby using the vector calculation method in accordance with the presentinvention;

FIG. 6 is a block diagram to show a configuration of the identificationjudgement circuit which is an application of the vector calculationmethod in accordance with the present invention;

FIG. 7 is an example Gray code conversion table;

FIG. 8 is a diagram to show a specific configuration of the maskgenerating circuit;

FIG. 9 is a chart to show a specific example of the conversion table forgenerating mask data M1;

FIG. 10 is a chart to show a specific example of the conversion tablefor generating mask data M2;

FIG. 11 is a block diagram to show a configuration of the vector searchdevice to search a vector closest to the input vector among pluralsearch target vectors;

FIG. 12 is to show an example of a modification for the identificationjudgement circuit; and

FIG. 13 is a diagram to show a configuration to make a comparisonbetween the input vector and the search target vector data.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The vector calculation device and the vector calculation methodaccording to the present invention extracts vectors which meet with asearch condition without a distance calculation when a search isconducted for the vector closest to the input vector among plural searchtarget vectors. By conducting a distance calculation between eachextracted search target vector and the input vector, the closest searchtarget vector to the input vector can be identified with a small amountof calculation. Reference will now be made in detail to the presentpreferred embodiments of the invention, examples of which areillustrated in the accompanying drawings.

FIGS. 1(A) to 1(D) are diagrams to describe an outline of the vectorcalculation method in accordance with the present invention. Forexample, the input vector A and the search target vector B are both 1storder vectors represented by 4 bits.

Generally speaking, when the input vector and search target vectors arecompared, a distance comparison between vectors can be conducted withhigh speed if the distance between vectors is judged either close or farby checking whether a data is a match or not without making a distancecalculation. As shown in FIG. 1(A), when the 1st order vector A withelements "1010" and the 1st order B with elements "1011" are compared,they do not match if all bits are compared. By masking the last positionbit, however, and comparing the first three bits, a match occurs.

FIG. 1(B) illustrates an example of expanding this data comparison to2nd order vectors. When only one component is considered, it can beconsidered exactly in the same manner as in the case of the 1st ordershown in FIG. 1(A).

For example, one component of the input vector A is A_(i), and onecomponent of the search target vector B is included in a range between(Ai-θi) and (Ai+θi). Then, the upper bits match, excluding the lower Pbits (one bit or plural bits are determined by θi) when each element Aiand Bi are displayed with bits. If each vector to be compared is morethan 2nd order, i.e. multiple order, then this kind of matchingidentification shall be conducted for each element.

As mentioned above, only the upper bits are compared for identificationjudgement. In binary code, however, all bits change by a difference ofan order of magnitude from q. For example as shown in FIG. 1(C), thebinary code for "7" is "0111" and the binary code for "8" is "1000", sothat even though the actual difference of the two data is "1", the upperbits do not match, and the data comparison by identification judgementof the upper bits cannot be conducted. For this reason, the presentinvention uses Gray codes which change only 1 bit if a change in datumto be compared is ±1. If an upper bit changes by an increase of an orderof magnitude, then the data comparison for each bit occurs afterexcluding the changed bit.

Referring to FIG. 1(D), in comparing the Gray codes of "7" and "8" whichare "0100" and "1100" respectively, if the lower three bits are comparedexcluding the variable bit (in this case the most significant bit), thenthe data which are close to each other match. In this way, whencomparing lower bits determined by a search range θ with the upper limitand the lower limit of the search range, mask those bits which vary,exclude those masked bits, and conduct matching evaluation of each ofthe corresponding bits. Thus, the search target vector B, which is closeto the input vector A, can be searched without conducting a distancecalculation.

FIG. 2 is a flow chart showing a specific processing procedure for thevector calculation method. FIG. 3 is a diagram to show a specificexample of a data comparison, with an example of conducting thecomparison of the first order vectors. The input vector A has theelement of "21", and the search target vector B has the element of "22"or "19". Now the vector calculation method in accordance with thepresent invention will be described with the reference to the flow chartin FIG. 2.

First, consider a case wherein Ai=21 and Oi=1. Each element A_(i) ofinput vector A is converted to Gray codes Ai!g (step 201). As shown inFIG. 3, if Ai=21, then it gets converted to corresponding Gray codes"11111."

Next, the first mask data M1i is created in order to mask those bitswhich change mutually when the upper limit and the lower limit of thesearch target range are compared (step 202). Ai minus 1 equals 20, andits Gray code becomes "11110". Also, Ai plus 1 equals 22, and its Graycode becomes "11101". When these two Gray codes are compared, makingthose bits which change as "0" and those bits which do not change as"1", "11100" is created as the first mask data M1i.

The second mask data M2i is created to mask lower bits determined inaccordance with θi (step 203). Specifically, by attaining an integer Pwhich satisfies 2^(p-2) <θi<2^(p-1), (P=0 if θ₂ =0), the second maskdata M2i making the lower P bits "0" and the remaining upper bits "1"which become "11110" is created. The relationship between θi and P is asfollows: if θi=2, then P=2, if Oi=3 or 4, then P=3, if θi=5˜8, then P=4.

Then, each element Bi of the search target vector B is converted to theGray codes Bi!g (step 204). A first search target vector B with theelement Bi as "22" is converted to the corresponding Gray code "11101".In steps 201 to 204, it is acceptable to start from any step as well asconducting a concurrent processing.

Thus, after obtaining Gray codes Ai!g and Bi!g for the data Ai and Bi,and the mask data M1i and M2i, a predetermined bit calculation (step205) occurs using those 4 data, and whether all bits are "0" or not isjudged (step 206). Specifically, bit by bit for the elements Ai of theinput vector A and the elements Bi of the search target vector B, an XORoperation for Ai! and Bi! is conducted, and to that result an ANDoperation is conducted for M1i and M2i.

The XOR operations judge whether the noted bits (bits not masked) matchor not. If the noted bits all match, then all the noted bits become "0".The XOR of M1i is to exclude, if the upper bits change when the upperlimit and the lower limit of the search target (Ai-θi and Ai+θi) arecompared, the changed bits from the object for the match processing, andby conducting the XOR the changed bits are forced to become "0". The XORof M2i is to exclude the lower bits which change within the range ofAi±θi from the object for the match processing, and by conducting theXOR the predetermined lower bits are forced to become "0".

By the above mentioned computation, if the predetermined bits decided bythe mask data M1i and M2i are forced to become "0", and other bits of Aiand Bi match, then all bits as the result of the computation become "0".

For example, when XOR is conducted for each bit of Ai="21" and Bi="22",then "00010" is attained as the result. Since M1i is "11100" and M2i is"11110", to conduct XOR for each bit of M1i and M2i means to force thelower two bits wherein at least one side is "0" to become "0", so thatthe end of result of the computation becomes "00000". Therefore, all thebits of the computation result are "0" and judged to be included withinthe range of Ai±θi (=20±1), and B is outputted as a vector to satisfythe search condition (step 207).

Then, the process determines if the search object vector which conductedthe above mentioned predetermined computation is a final vector or not(step 208), i.e. whether there are other search target vectors whichhave not finished the predetermined calculation. The process repeatsstep 204 until the process for all the search target vectors arecompleted.

For example, if a second search vector B having an element Bi=19 exists,the element Bi is converted to the Gray code at step 204, and at step205 XOR is conducted for each bit of Bi and Ai in Gray codes. Morespecifically, the Gray code of Bi (=19) is "11010"; the Gray code of Ai(=21) is "11111"; and the result of conducting the XOR for each bit is"00101". Consequently, by forcing the lower two bits which aredetermined by M1i and M2i to become "0" the final result, "00100", isattained. In this case, not all the bits are "0" so that it is not avector to satisfy the search condition, and it will not be outputted atstep 207.

In this way, for each element of the two vectors to be compared, onlypredetermined bits are masked, and by conducting the matching for eachcorresponding bit, whether the elements of one vector are includedwithin a certain range centered on the elements of the other vector isjudged.

FIG. 4 is a table showing a searchable range of the search targetvectors by using the computation method in accordance with the presentinvention, with an example of the elements Ai of the first order vectorbeing "21".

As mentioned above, when θi=1 by comparing the respective Gray codes of"20" and "22", M1 becomes "11100" and the integer P to satisfy 2^(p-2)<θ<2^(p-1) is "1" M2i becomes "11110".₅₁ M1i-M2i is "11100", and thelower two bits are masked. Consequently, the search target vector B,with an element Bi having upper three bits all "0" when XOR isconducted, is the vector which satisfies the search condition Ai±1.

In FIG. 4, the range a is the range having upper three bits all "0" whenthe above mentioned XOR is conducted, so that the search target vectorsB having Bi=20, 21, 22, and 23 are found to have satisfied the searchcondition.

In the same manner, when θi=2 by comparing the respective Gray codes of19 and 23, M1i becomes "01001" and the integer P to satisfy 2^(p-2)<θ≦2^(P-1) is "2". Thus, M2i becomes 11100. M1i-M2i is 01000, and thelower three bits are masked. Consequently, the search target vector B,having element Bi whose upper two bits are both "0" when the XOR isconducted, is a vector which satisfies the search condition Ai±2.

In FIG. 4 the range shown with area b is, when above mentioned XOR isconducted, where upper two bits become "0", and the search target vectorB which is in the range of Bi=16 to 23 is searched as meeting with thesearch condition.

FIG. 5 is a table that shows a searchable range of search target vectorsusing a computation method in accordance with the present invention. Anexample of an element Ai of the first order vector is "15". When Ai=15,and i=1 or 2, the highest bit of the element Bi of the search targetvector B changes when Bi is 15 or 16.

When θi=1, by comparing Gray codes of "14" and "16", M1i becomes 01110and integer P to meet 2^(p-2) <θ<2^(p-1) is "1. Thus, M2i becomes 11110.M1i-M2i is 01110, and both the highest bit and the lowest bit(altogether two bits) are masked. Consequently, the search target vectorB with elements Bi having remaining all three bits "0" when XOR isconducted, is a vector filing the search condition of Ai±1.

In FIG. 5, the area c is a range wherein all middle three bits become"0" when XOR is conducted. The search target vector B as Bi=14, 15, 16,or 17 to all meet the search condition.

In the same manner, when θi=2, by comparing the Gray codes of "13" and"14", M1i becomes "01101", and the integer P to satisfy 2^(p-2)<θ<2^(p-1) is 2. Thus, M2i becomes 11100. M1i-M2i becomes "01100", andthe two lower bits and the highest bit (altogether three bits) aremarked. Consequently, the search target vector B with elements Bi havingthe second and third bits from the highest to be "0" is the vectormeeting the search condition of Ai±2.

In FIG. 5, area d is the range wherein the second and third bits fromthe highest are "0" after XOR is conducted, and the search target vectorB in the range of Bi=12˜19 meets the search condition.

In this way, a vector close to the input vector A is searched from theplural search target vectors B, by the vector computation method inaccordance with the present invention, without conducting a complexcomputation on each element of the vectors A and B to be compared. Theprocess judges whether the search condition is meet or not by checkingwhether predetermined bits match or not, which reduces the burden ofprocessing and thereby shortens the processing time.

According to the present method of vector computation, the predeterminedbits are masked when two data Ai and Bi are compared. This leads tosearching a broader range Bi than original range Ai±θi. If a limitednumber of vectors which meet with a search condition are extracted outof numerous search target vectors, then by conducting the distancecalculation between the extracted plural search target vectors and theinput vector, a more accurate search can be conducted.

Even in case the distance calculation is conducted at the last step, byusing the vector calculation method in accordance with the presentinvention, the search target vectors for the distance calculation arenarrowed down, thereby reducing the processing burden as well asshortening the processing time.

The above mentioned example dealt with the case for the first ordervectors A and B. The same principle can be also applied to multipledimensional vectors above the second order by making comparison betweeneach element.

FIG. 6 is a schematic diagram of a configuration of an identificationjudgement circuit 10, a computation device that applies a vectorcomputation method in accordance with the present invention.

The identification judgement circuit 10, shown in FIG. 6, includes twoGray code conversion circuits 12 and 14 that convert input data to Graycodes. Two mask generating circuits 16 and 18 generate mask data M1 andM2. An XOR circuit 20 conducts XOR for each bit of the two Gray codesfrom the two Gray code conversion circuits 12 and 14. An AND circuit 22conducts an AND for each bit of the output data from the XOR circuit 20and the mask data M1 and M2.

The Gray Code conversion circuit 12 receives an element data Ai of theinput vector A and outputs the corresponding predetermined bits Graycodes. The Gray code conversion circuit 14 receives element data Bi ofthe search target vector B and outputs the corresponding predeterminedbits Gray codes. For example, if an element Ai of the input vector A is"21" and the corresponding element Bi of a search target vector B is"20", the Gray code conversion circuit 12 outputs a 5 bit Gray code"11111" corresponding to Ai(=21). The Gray code conversion circuit 14outputs a 5 bit Gray code "11110" corresponding to Bi (=20).

Each Gray code conversion circuit 12 and 14 possesses a memory such as aROM storing a Gray code conversion table. When a predetermined bitbinary code corresponding to Ai or Bi is inputted as an address of thismemory, a corresponding Gray code is outputted as data.

FIG. 7 shows an example Gray code conversion table. Each addresscorresponds to a 5 bit binary code, and the stored data correspond to 5bit Gray code. For example, for the address corresponding to Ai=21, theGray codes stored in the corresponding range, "11111" is outputted.

The mask generating circuit 16 generates mask data M1. This mask data M1is generated at step 202 in FIG. 2. If ±θi centered on an element Ai ofthe input vector A is to be a search range, it is to mask the variablebits when the upper limit and the lower limit of this search range arecompared.

FIG. 8 is a diagram to show a configuration of the mask generatingcircuit 16. In the mask generating circuit 16, an ADD circuit 30 adds anelement Ai of the input vector A to data θi to specify the search rangeof the element Ai. A subtraction circuit 32 subtracts Ai from Ai tocompute Ai-θ. Two Gray code conversion circuits 34 and 36 convert therespective computed result to predetermined bit (5 bits if the Gray codebits corresponding to Ai are 5 bits) Gray codes. An XNOR circuit 38attains the XOR for each bit of the two Gray codes converted by the twoGray code conversion circuits 34 and 36 and inverts the result.

If Ai=21 and Bi=1, Gray code conversion circuit 34 outputs the Graycodes "1101" corresponding to Ai+θi=22. The Gray code conversion circuit36 outputs the Gray codes "11110" corresponding to Ai-θi=20.Consequently, when each bit of these two Gray codes are compared, theXNOR circuit 38 outputs the mask data M1, "11100", wherein "0"represents corresponding bits being different, and "1" represents thecorresponding bits being the same.

The mask generating circuit 16 can also be configured, for example, witha conversion table like the Gray code conversion circuit 12, as well asthe configuration shown in FIG. 8. FIG. 9 shows an example of aconversion table to generate mask data M1. For example, the binary codes"10101" corresponding to Ai=21, and the predetermined bits (e.g. 2 bits)data "01" corresponding to θi=1 are inputted as an address. In thecorresponding range, "11100" is stored as the mask data M1, andresponding to the above mentioned address designation, this mask data M1is read and outputted.

The mask generating circuit 18 generates the mask data M2. This maskdata M2 is generated at step 203 in FIG. 2 to mask the lower bits whichchange in the search range ±θi. When θi is inputted, an integer P isdetermined which satisfies 2^(p-2) <θ≦2^(p-1) (P=0 if θ=0). Then, maskdata M2, which has the same number of bits as the Gray codecorresponding to Ai, comprising P lower bits being "0" and the remainingupper bits being "1", is outputted. For example, if θi=1, the integer Pto satisfy the above mentioned inequality is 1, so that the mask data M2has "0" only in the lowest bit as in "11110".

The integer P can be determined either by calculation or, as in the Graycode conversion circuits 12, by converting θi to mask data M2 throughthe use of a conversion table stored in a memory.

FIG. 10 shows a conversion table to generate mask data M2. If θi is tobe expressed in 3 bits, then, for example, a binary code "001"corresponding to θi=1 is inputted as an address.

In the corresponding range, "11110" is stored as the mask data M2. Then,responding to the above mentioned address designation, the mask data M2is read and output.

The XOR circuit 20 receives the Gray codes Ai!_(g) from the Gray codeconversion circuit 12 and the Gray codes Bi!_(g) from the Gray codeconversion circuit 14. The XOR circuit 20 conducts XOR for each bit. TheAND circuit 22 receives this XOR output and the two mask data M1 i andM2i, and conducts AND for each bit. By these two circuits thecomputation shown in step 205 in FIG. 2 is conducted.

Consequently, when all the outputted bits of the AND circuit 22 are "0"the element Bi of the search target vector B is included within apredetermined range decided by θi centered on Ai of the input vector A.On the contrary, if at least one bit out of the output of the ANDcircuit 22 is "1", then element Bi of the search target vector B is notincluded in the above mentioned predetermined range. In this way, theidentification judgement circuit 10 conducts a judgement whether Bi isincluded in the predetermined range centered on Ai when an element Ai ofthe input vector A and an element Bi of the search target vector B areinputted through the identification judgement by a simple processing.

In the above mentioned description for the identification judgementcircuit 10, plural Gray code conversion circuits 12 and 14, whichconduct the same processing, are provided. One common Gray codeconversion circuit can replace the two Gray code conversion circuits 12and 14 through a time shared system.

So far the operation of the identification judgement circuit 10 whichfocuses on either element of the input vector A or the search targetvector B has been described. When plural elements are processedsimultaneously, it is acceptable to either repeat the processing bit bybit by the identification judgement circuit 10, or after conducting theGray code conversion for each element, then conduct a processing for allbits by the XOR gate 20 and the AND gate 22. In this case, thecomparison between the input vector A and one search target vector B canbe done in one time processing.

FIG. 11 is a diagram to illustrate a configuration of a vector searchdevice to search for the closest vector to the input vector among pluralsearch target vectors. The vector search device shown in FIG. 11comprises an identification judgement circuit 10a, a distancecomputation circuit 40, and a minimum value judgement circuit 42.

The identification judgement circuit 1 Oa is a variation of theidentification judgement circuit 10 shown in FIG. 6 in order to conductthe identification judgement for all elements of both the input vector Aand the search target vector B. As an example, suppose the input vectorA and the search target vector B are n-order vectors respectively andeach element is expressed with m-bits.

The identification judgement circuit 10a comprises two Gray codeconversion circuits 12a and 14a, two mask generating circuits 16a and18a, an XOR gate 20a, and an AND gate 22a.

The Gray code conversion circuit 12a corresponds to the Gray codeconversion circuit 12 shown in FIG. 6. The Gray code conversion circuit12a receives n-number element data of the input vector A and outputs atotal of n*m bit data through converting to m-bit Gray codes for eachelement.

The Gray code conversion circuit 14a corresponds to the Gray codeconversion 14 in FIG. 6. The Gray code conversion circuit 14a receivesn-number element data of a search target vector B and outputs a total ofn*m bit data through converting to m-bit Gray codes for each element.

The mask generating circuit 16a corresponds to the mask generatingcircuit 16, and based on θi which is set for each element of the inputvector A and each element data Ai of the input vector A, outputs themask data M1 with m-bits for each element, altogether n*m bits.

The mask generating circuit 18a corresponds to the mask generatingcircuit 18 shown in FIG. 6, and based on θi which is set for eachelement of the input vector A, outputs the mask data M2 with m-bits foreach element, altogether n*m bits.

In this manner, the Gray code conversion corresponding to the n-numberelements of the input vector A and the search target vector B, and thegeneration of the mask data M1 and M2 are conducted in parallel. Theidentification judgement for all elements are conducted simultaneouslyby XOR gate 20a and AND gate 22a.

Consequently, when each element of the search target vector B isincluded within a range of θi which set for each element of the inputvector A, all the bits of the n*m bits data outputted from theidentification judgement circuit 10a become "0".

The distance computation circuit 40 shown in FIG. 11 computes thedistance between the input vector A and the search target vector B whenall the bits of the outputted data of the identification judgementcircuit 10a are "0". Among computation distances, there are, forexample, Euclid distance and Manhattan distance, etc. The minimum valuejudgement circuit 42 conducts the minimum value judgement based on thecomputation result of the distance calculation circuit 40, and extractsthe search target vector B which has the minimum distance.

In this way, through a simple identification judgement by theidentification judgement circuit 10a, the range of the search targetvector B close to the input vector A is narrowed down from plural searchtarget vectors B. Then, distance computation occurs between the narroweddown search target vector B and the input vector A to find the searchvector B which has the smallest distance. Consequently, even if thereare a lot of numbers in the search target vector B, by conducting thesimple identification judgement, the number of the search target vectorsB for the distance computation will be drastically reduced. Thus, theburden of the search processing to find the one close to the inputvector among plural search target vectors will be reduced and itsprocessing time can be shortened.

FIG. 12 is a diagram of a variation of the identification judgementcircuit using a Content Addressable Memory LSI. An identificationjudgement circuit 50 shown in FIG. 12 includes two Gray code conversioncircuits 12a and 14a; two mask generating circuits 16a and 18a, as shownin FIG. 11; and the Content Addressable Memory LSI 52. The ContentAddressable Memory LSI 52 checks the content of the Gray codescorresponding to all the elements of the previously stored search targetvector B, when the Gray codes corresponding to all the elements of theinput vector A are inputted in parallel and is able to conduct theidentification judgement only for the plural bits excluding the maskeddata by the mask data M1 and M2.

The Content Addressable Memory LSI 52 needs to convert each element ofthe wanted search target vector B for the identification judgement toGray codes by the Gray code conversion circuit 14a and store them inadvance.

In this way, the Content Addressable Memory LSI 52 allows theidentification judgement for each element of the input vector A and thesearch target vector B with high speed. The hardware configuration ofthe Content Addressable Memory LSI 52 determines the processing speed.In general, it is possible to conduct the identification judgement up toseveral k bits plural bits data, so that even multiple order vectors canbe handled for the identification processing with all elements as targetfor the high speed processing.

The distance computation circuit 40 and the minimum value judgementcircuit 42 shown in FIG. 11 may be connected to the back part of theContent Addressable Memory LSI 52. The distance calculation for theinput vector A is only conducted for those search target vectors B thatthe identification of all the bits the Content Addressable Memory LSI 52pays attention to have been verified. Then, the search target vector Bwhich has the minimum distance is extracted.

Other embodiments of the invention will be apparent to those skilled inthe art from consideration of the specification and practice of theinvention disclosed herein.

Though the above mentioned embodiments describe examples of expressingeach element of the input vector A or the search target vector B in 4bits or 5 bits, the elements may be expressed with less than 3 bits ormore than 6 bits.

The sixth bit Gray code can be attained by describing the 5 bit Graycodes shown in FIG. 7 arranged symmetrically between top and bottom andthen assigning "0" to the top of the first 32 and "1" to the top of theremaining 32. Through the same process, Gray codes above 7 bits can beattained.

The above described embodiments illustrate examples of converting binarycodes to Gray codes using a conversion table of, for example, the Graycode conversion circuit 12. It is also acceptable to use a logicaloperation for the conversion. More specifically, Gray codes can beattained by conducting XOR for each bit of the binary codes for theconversion target and the data after shifting the binary code to theright 1 bit. For example, the binary code of "21" is "10101". The dataattained by shifting the binary code to the right 1 bit is "01010". Byconducting XOR for each bit of these two data, the Gray codecorresponding to "21" is attained as "11111".

In the above mentioned embodiment, a comparison of each element betweenthe input vector A and the search target vector B is conducted, but ifit is the first order vector then it becomes simply a comparison ofnumeric data.

For bits other than those bits designated by the first and the secondmask data, a comparison for each element of the input vector and thesearch target vector expressed as Gray codes is conducted, and by asimple bit operation the search field is narrowed.

According to the present invention, the distance between two vectors iscomputed only when all the elements of the input vector and the searchtarget vector are judged to have met with the search condition, judgingthe minimum value of the distance if there are plural search targetvectors. Compared with computing the distance between all the searchtarget vectors and the input vector, the burden of the processing tosearch for the search target vector which has the minimum distance isreduced and the processing time is shortened.

Other embodiments of the invention will be apparent to those skilled inthe art from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with the true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A vector computation device for receiving aninput vector and for determining whether one element of a search targetvector is within a predetermined search range of one element of theinput vector, the search range having an upper limit value and a lowerlimit value bracketing the input vector, the device comprising;a firstGray code conversion means for converting the one element of the inputvector to a first Gray code; a second Gray code conversion means forconverting the one element of the search target vector to a second Graycode; a first mask generating means for generating first mask data bycomparing Gray codes corresponding to the upper limit value and thelower limit value, the first mask data indicating the similaritiesbetween the Gray codes corresponding to the upper limit value and thelower limit value; a second mask generating means for generating secondmask data by calculating the number of bits corresponding to the size ofthe search range; and means for determining whether the one element ofthe search target vector is within the search range by comparing theresults of XOR operation between the first and the second Gray codes tothe first and second mask data.
 2. The vector computation device asclaimed in claim 1, wherein the first and the second Gray codeconversion means include means for performing an XOR operation betweenthe input data binary code and a binary code corresponding to the inputdata binary code shifted one bit to the right.
 3. The vector computationdevice as claimed in claim 1, wherein the first and the second Gray codeconversion means comprise a conversion table storing the correspondencebetween vectors and Gray codes.
 4. The vector computation device asclaimed in claim 1, wherein said first mask generating means comprises;athird Gray code conversion means for converting the upper limit value ofthe search range to a third Gray code; a fourth gray code conversionmeans for converting the lower limit of the search range to a fourthGray code; and means for performing an XOR operation between the thirdGray code and the fourth Gray code.
 5. The vector computation device asclaimed in claim 1 wherein the first mask generating means comprises aconversion table storing the search range of the input vector.
 6. Thevector computation device as claimed in claim 1, wherein the second maskgenerating means determines an integer P wherein 2^(p-2) <θ≦2^(p-1) andwherein -θ to +θ is the search range.
 7. The vector computation deviceas claimed in claim 6, wherein the second mask generating meanscomprises a conversion table storing the correspondence between theinteger P and the search range.
 8. The vector computation device asclaimed claim 1 further comprising;a distance computation means forcomputing the distance between the input vector and the search targetvector when all elements of the input vector and the search targetvector are within the predetermined search range; and a minimum valuejudgement means for judging the minimum value out of the distancescalculated by said distance calculation means when more than one searchtarget vector is within the predetermined search range.
 9. A vectorcomputation method for determining whether one element of a searchtarget vector is within a predetermined search range of one element ofan input vector, the search range having an upper limit value and alower limit value bracketing the input vector, the method comprising thesteps of:converting the one element of the input vector into a firstGray code; converting the one element of the search target vector into asecond Gray code; generating mask data based on the upper limit valueand the lower limit value; comparing the first Gray code to the secondGray code to obtain a first comparison result; and comparing the firstcomparison result to the mask data.
 10. The method as claimed in claim9, wherein the step of converting the one element of the input vectorinto a Gray code includes the sub-step of accessing a look up tablestored in a memory device.
 11. The method as claimed in claim 10,wherein the step of converting the one element of the search targetvector into a Gray code includes the sub-step of accessing a look uptable stored in a memory device.
 12. The method as claimed in claim 9,wherein the step of generating mask data includes the sub-step ofaccessing a look up table stored in a memory device.
 13. The methodaccording to claim 9, wherein the step of comparing the first Gray codeto the second Gray code includes the sub-step of inputting the firstGray code and the second Gray code, bit-by-bit, into an XOR logic gate.14. The method according to claim 9, wherein the step of comparing thefirst comparison result to the mask data includes the sub-step ofinputting the first Gray code and the second Gray code, bit-by-bit, intoan AND logic gate.
 15. A vector computation method for determiningwhether one element of a search target vector is within a predeterminedsearch range of one element of an input vector, the search range havingan upper limit value and a lower limit value bracketing the inputvector, the method comprising the steps of:converting the one element ofthe input vector into a first Gray code; converting the one element ofthe search target vector into a second Gray code; generating mask databased on the upper limit value and the lower limit value; calculatingthe XOR operation of the first Gray code and the second Gray code; andcalculating the AND operation of the result of the XOR operation and themask data.
 16. A vector computation method for determining whether oneelement of a search target vector is within a predetermined search rangeof one element of an input vector, the search range having an upperlimit value and a lower limit value bracketing the input vector, themethod comprising the steps of:converting the one element of the inputvector into a first Gray code; converting the one element of the searchtarget vector into a second Gray code; generating first mask data basedon the upper limit value and the lower limit value; generating secondmask data based on the extend of the search range; calculating the XORoperation of the first Gray code and the second Gray code; andcalculating the AND operation of the result of the XOR operation, thefirst mask data, and the second mask data.